A data processing system includes a central processing unit (CPU) that executes instructions and thereby manipulates data. The instructions and data are stored in a memory system, which is typically isolated from the CPU. The CPU interacts with the memory system through a memory interface. The functioning of the memory interface is predominantly under the control of the CPU, and is typically performed by a memory controller. The memory controller can be integrated tightly with the CPU, such as on the same silicon chip as the CPU, or it can be included with other components of the data processing system, one such component often referred to as a north-bridge chip.
There are many types of memory. One type is referred to as dynamic random access memory (DRAM). A DRAM system can include several known types of DRAM, of which double data rate (DDR) is an example. The memory controller that governs the interface to the DRAM system may thus be referred to as a DRAM controller. Furthermore, a memory controller that interfaces a CPU to DDR DRAM may be referred to as a DDR DRAM controller.
DDR DRAM conforms to industry standard electrical and protocol standards set forth by the Joint Electron Devices Engineering Councils (JEDEC). These standards define how the contents of the DRAM are accessed (read), and stored (written). The original DDR standard has recently been enhanced to include standards known as DDR2 and DDR3. The interface to any of these DDR DRAMs is accomplished primarily through two signal classes, DQ (data) and DQS (data strobe).
The JEDEC standard interface specifies that during a read operation, the DDR DRAM will issue these two signal classes at the same time, a manner commonly referred to as “edge aligned.” In order for the DRAM controller to correctly acquire the data being sent from the DDR DRAM, the DRAM controller typically utilizes a delay-locked loop (DLL) circuit to delay the DQS signal so that it can be used to correctly latch the DQ signals. Topological and electrical difference between DQ and DQS interconnects result in timing skew between these signals, making it difficult to establish a proper delay for the DLL. For similar reasons, the DRAM controller also utilizes DLL circuits to support the writing of data to the DDR DRAM.
The timing delays provided by the DLL circuits can be determined during development of the product wherein these delays are fixed and independent of final product configuration differences. One often refers to such a technique as “dead reckoning.” This is suboptimal since the final product and associated components will affect the timing relationships of the memory interface signals. Alternatively, the timing delays provided by the DLL circuits can be customized for each design configuration each time the device is turned on, by executing a training program. The training program is typically a software program stored in a basic input/output system (BIOS) memory device, but it can also be implemented within the device hardware. The training program executes an algorithm, which determines appropriate timing delays associated with each memory interface signal.
Moreover, memory chips now operate at far higher speeds than the speeds of the original DDR DRAMs. These speeds are now so high that signal propagation delays between the DRAM controller and the memory chips can exceed one memory clock (MEMCLK) cycle. At such high speeds, training the timing delays becomes more difficult.